

//Stage one: Select one or the other:
module Select1(In0, In1, Signal, Out);
	input [15:0] In0, In1; //assuming we use the codec with 16-bit A/D, D/A.
	input Signal;
	output [15:0] Out;
	
	always
	case (Signal)
		0 : Out = In0;
		1 : Out = In1;

	end

endmodule



// Stage two: Split half and half between two inputs:
module HalfEach(In0, In1, Out);
	input [15:0] In0, In1;
	output [15:0] Out;
	
	always
	half0 = In0 / 2;
	half1 = In1 / 2;
	
	Out = half0 + half1;
	
	end
	
endmodule



// Stage three: controllable levels allow 50/50 - 60/40 - 70/30 etc for two channels
module Mix1(In0, In1, Mix, Out);
	input [15:0] In0, In1;
	input [3:0] Mix; //8-bit ADC on a POT. (These are going to be the switches on the board, just hook them up as a 3 or 4 bit with 3/4 switches)
	output [15:0] Out;
	
	always
	//Check the value for the POT
	
	//Scale each signal according to the value of the POT
	
	//Add the scaled signals
	
	//Done
endmodule	


//Stage four.this: incorporate an ability to loop some audio and play it back from that channel.
// module Loop0(In0, SaveLoop, PlayLoop, Out);
	// input [15:0] In0;
	// input SaveLoop, PlayLoop;
	// output [15:0] Out;
	
	// always @ (SaveLoop)
		// if SaveLoop : 
	 // Check for Loop Flag
	 // When Loop Flag is high, start saving data
			// Need to look up how to actually save data on the FPGA. Shouldn't be too hard, it has built-in memory
			// Ideally this handles the problem of running out of memory by either (a) stopping saving, or (b) throwing out the front and still saving. Just don't error out.
	 // When Loop Flag is low, stop saving data
	
	// always @ (PlayLoop)
	 // Check for Play Flag
	 // When Play Flag is High, play the saved data. LOOP IT.
	 // When Play Flag is Low, play the data on In0.
	 
	// This happens before and in addition to the mixer/mux.
	


//Stage four.that: select the chanel that has the louder stuff on it, and play that one.

//Stage five: if the level on a channel spikes, then don't let it actually spike so high.


//FPGA should be slave, other is master, check out FPGA for fun for SPI interfaces.